Security concerns and communications issues such as deadlock within on-chip networks have encouraged users to adopt formal verification in more focused ways. However, its performance depends greatly on the type of logic on which it is deployed and the way it is applied. Formal verification is potentially very fast because it does not have to evaluate every possible state to demonstrate that a given piece of logic meets a set of properties under all conditions. Sphere: Technologies | Tags: assertions, clock domain crossing (CDC), coverage driven verification, equivalence checking, formal verification, model checking, PSL, X propagationįormal verification is the overarching term for a collection of techniques that use static analysis based on mathematical transformations to determine the correctness of hardware or software behavior in contrast to dynamic verification techniques such as simulation.Īs design sizes have increased and with them simulation times, verification teams have looked for ways to reduce the number of vectors needed to exercise the system to an acceptable degree of coverage.
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